The present disclosure relates to a storage control apparatus, a storage apparatus, and an information processing system that correct error detection and correction in a memory, a processing method therein, and a program that causes a computer to execute the processing method.
In a storage apparatus including a non-volatile memory and a memory controller that controls the non-volatile memory, the memory controller generates, for each writing unit, an error detection and correction code (ECC) with respect to data input to improve the properties for storing data. On the memory, data and ECC parity is stored in relation to each other. When the data is read, also the ECC parity is read together with the data. The data on which a bit error detection process and a bit error correction process are performed is output. The properties for storing data of a cell of a non-volatile memory are deteriorated as the number of writing times increases. Therefore, using an ECC with higher correction capabilities results in enhancement of the reliability. On the other hand, because the size of parity for protecting the same wiring unit increases if the correction capabilities are high, it needs to expand capacity for storing ECC parity, resulting in increase in cost.
In view of the above, it has been proposed to improve the reliability of data by preparing a second ECC with high correction capabilities for protecting a plurality of writing units in addition to a first ECC for protecting a predetermined writing unit in the past (see, for example, Japanese Patent Application Laid-open No. 2011-081776).